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rf amp & servo signal processor s1l922 5x 1 introduction as a pre-signal & servo signal processor for the disc-man, s1l9225x is a low voltage, low consumption current ic that can read cd-rw, and cd-r discs and can be applied to various products, such as the cdp/vcd/cd-mp3 for the disc-man. it is a hard-wired free-adjustment servo, which automatically controlled the control point of the pre-signal portion. features ? rf amplifier (cd, cd-r, cd-rw applicable) ? gain setting & monitoring for the cd-r, cd-rw disc ? focus error amp & febias adjustment ? tracking error amp & balance, gain adjustment ? fok, defect, mirror detect ? center voltage amplifier ? apc (automatic power control) ? apc laser controller (controlled by tracking summing signal) ? rf agc & eq control (agc level control compatible) ? e nhanced efm slice (double asymmetry method) ? focus servo loop & offset adjustment ? tracking servo loop & offset adjustment ? sled servo loop ? spindle servo loop ? auto-sequence ? fast search mode (1 - 36000 track jump) ? interruption countermeasure ? focus & tracking servo muting controlled by efm duty check ? rf peaking prevention system by efm duty check ? focus, tracking, spindle loop pole move option ? operating voltage 2.7v ? 3.3v ? power saving mode lpc control used by side beam signal, it related to pick-up assurance. when used pick-up, the specification is present extra. ordering information device package supply voltage operating temperature s1l9225x01 ? q0r0 64-lqfp-1414 2.7v ? 3.3v -20 c ? +75 c 64-lqfp-1010
s1l9225x rf amp & s ervo signal processor 2 block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 rf agc & eq control focus ok detect defect detect mirror gen center voltage apc. laser control & lpc tracking servo loop - gain & phase compensation - track jump - offset adjust - tzc gen. tracking error (rw) i/v amp rf & focus error (cd-rw) i/v amp hardware logic - auto-sequencer - fast search - febias, focus servo, tracking offset adj. - tracking balance & gain adjust - interruption detect - efm muting system sled servo & kick gen spindle servo lpf efm comparator micom data interface logic decoder focus servo loop - gain & phase compensation - focus search - offset adjust - fzc gen. eqo efmi dcc1 dcc2 mcp dcb vssa/gnd frsh fset flb fgd fdfct fse0 fsi atsco tgu pd ld lpft2 lpft1 teio tzc atsc teo tem slp slo slm feo fem spdlo spdlm eqi rfo rfm rfm2 teso lpc lpb eqc vcc vref pde pdf pdd pdb pdc pda vdda istat2 istat1 mck mdata mlt reset wdck clvi lock asy efm2 efm sstop vss vdd eqo
rf amp & servo signal processor s1l922 5x 3 application diagram s1l9225x to micom from micom 120k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 pd ld lpft2 lpft1 teio tzc atsc teo tem slp slo slm feo fem spdlo spdlm vdda istat2 istat1 mck mdata mlt reset wdck clvi lock asy efm2 efm sstop vss vdd eqo efmi dcc1 dcc2 mcp dcb vssa/gnd frsh fset flb fgd fdfct fseo fsi atsco tgu eqo 821 47pf 333 103 103 4.7uf 104 104 104 102 104 from micom to micom from micom from micom from dsp 333 474 1m 20k 8.2k fsw smds smdp 10k from dsp 474 103 to dsp from_pick-up 47k 381 56k 103 15k 100k 39k 474 120k 683 10uf 222 333 150k 103 103 103 100uf 3v 22 1uf a eqi rfo rfm rfm2 teso lpc lpb eqc vcc vref pde pdf pdd pdb pdc pda b c d e f 500 100 3v 1k 3.6uf 33uf 683 2.2uf 82pf 12pf 22k 8pf 153
s1l9225x rf amp & s ervo signal processor 4 pin configuration s1l9225x 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 eqo efmi dcc1 dcc2 mcp dcb vssa/gnd frsh fset flb fgd fdfct fse0 fsi atsco tgu pd ld lpft2 lpft1 teio tzc atsc teo tem slp slo slm feo fem spdlo spdlm eqi rfo rfm rfm2 teso lpc lpb eqc vcc vref pde pdf pdd pdb pdc pda vdda istat2 istat1 mck mdata mlt reset wdck clvi lock asy efm2 efm sstop vss vdd eqo
rf amp & servo signal processor s1l922 5x 5 pin description table 1. pin description pin no symbol i/o description 1 eqo o rf equalizer output 2 efmi i efm slice input. (input impedance 47k) 3 dcc1 o time constant connection output to detect defects 4 dcc2 i time constant connection input to detect defects 5 mcp i cap connection terminal for mirror hold 6 dcb i cap terminal to limit defect detection 7 vssa/gnd g rf, servo ground 8 frsh i cap connection terminal for focus search 9 fset i filter bias for focus, tracking, spindle 10 flb i cap terminal to make focus loop rising low band 11 fgd i terminal to change the high frequency gain of the focus loop 12 fdfct i cap connection terminal to integrate the focus error 13 fseo o focus error output 14 fsi i focus servo input 15 atsco o shock level detect output (shock: l: state) 16 tgu i time constant connection to change the high frequency gain of the tracking loop. 17 vdda p power supply for the servo 18 istat2 o internal status output pin (fok, trcnt) 19 istat1 o internal status output pin 20 mck i micom clock pin 21 mdata i data input pin 22 mlt i data latch input pin 23 reset i reset input pin 24 wdck i 88.2khz input terminal from dsp 25 clvi i control output input terminal of dsp spindle 26 lock i sled run away prevention pin (l: sled off and tracking gain up) 27 asy i auto asymmetry control input terminal 28 efm2 o output for efm pulse integration 29 efm o efm output terminal for rfo slice (to dsp) 30 sstop i pick up's maximum lead-in diameter position check pin 31 vss g digital ground 32 vdd p digital power
s1l9225x rf amp & s ervo signal processor 6 table 1. pin description (continued) pin no symbol i/o description 33 spdlm i spindle amp inverting input pin 34 spdlo o spindle amp output pin 35 fem i focus servo amp inverting input pin 36 feo o focus servo amp output pin 37 slm i sled servo inverting input 38 slo o sled servo output 39 slp i sled servo non inverting input 40 tem i tracking servo amp inverting input pin 41 teo o tracking servo amp output pin 42 atsc i anti-shock input pin 43 tzc i tracking zero crossing input pin 44 teio b tracking error output & tracking servo input pin 45 lpft1 i tracking error integration input terminal 1 (automatic control) 46 lpft2 i tracking error integration input terminal 2 (automatic control) 47 ld o apc amp output pin 48 pd i apc amp input pin 49 pda i photo-diode a/c rf i/v amp1 inverting input pin 50 pdb i photo-diode b/d rf i/v amp2 inverting input pin 51 pdc i photo-diode a/c rf i/v amp1 inverting input pin 52 pdd i photo-diode b/d rf i/v amp2 inverting input pin 53 pdf i photo-diode f with tracking (f) i/v amp inverting input pin 54 pde i photo-diode e with tracking (e) i/v amp inverting input pin 55 vref o (vcc+gnd)/2 voltage reference output pin 56 vcc p rf part vcc power supply pin 57 eqc i agc_ equalize level control terminal and vca input connection cap terminal 58 lpb i laser power level control resistance terminal 59 lpc i laser power control tracking summing signal integration terminal 60 teso o tracking error summing signal 61 rfm2 i rf summing amp 2x filter on/off 62 rfm i rf summing amp inverting input terminal 63 rfo o rf summing amp output terminal 64 eqi i rfo dc control input terminal (use by mirror, fok, agc&eq terminals)
rf amp & servo signal processor s1l922 5x 7 maximum absolute ratings item symbol rating unit power supply voltage v dd -0.3 ? 5.5 v input supply voltage v i -0.3 ? v dd + 0.3 v operating temperature t opr -20 ? 75 c storage temperature t stg -40 ? 125 c
s1l9225x rf amp & s ervo signal processor 8 electrical characteristics table 2. electrical characteristics no. inspection items symbols inspection block spec unit 1 supply current 2.7v iccty 6 10 14 ma 2 rf amp offset voltage vrfo rf amp -85 0 +85 mv 3 rf amp oscillation voltage vrfosc 0 50 100 mv 4 rf amp voltage gain ac grfac 16.2 14.7 17.7 db 5 rf amp voltage gain bd grfbd 16.2 14.7 17.7 db 6 rf rhd characteristic rfthd - - 5 % 7 rf amp maximum output voltage vrfh 2.35 - - v 8 rf amp minimum output voltage vrfl - - 0.85 v 9 rf cdrw gain ac1 grwac1 5.5 7.7 9.9 - 10 rf cdrw gain ac2 grwac2 11.0 13.1 16.2 - 11 rf cdrw gain ac3 grwac3 18.0 21.3 24.6 - 12 rf cdrw gain bd1 grwbd1 5.5 7.7 9.9 - 13 rf cdrw gain bd2 grwbd2 11.0 13.1 16.2 - 14 rf cdrw gain bd3 grwbd3 18.0 21.3 24.6 - 15 rf ivsel connection ac rfselac 24 47 70 k w 16 rf ivsel connection bd rfselbd 24 47 70 k w 17 rf amp offset conversion 1 vrfoff1 0 -100 -200 mv 18 rf amp offset conversion 2 vrfoff2 -100 -200 -300 mv 19 focus error offset voltage vfeo1 focus error -525 -250 -50 mv 20 focus error auto voltage vfeo2 amplifier -35 0 +35 mv 21 istat state after febias control vistat1 2.5 - - v 22 focus error voltage gain 1 gfeac 18 21 24 db 23 focus error voltage gain 2 gfebd 18 21 24 db 24 focus error voltage gain difference d gfe -3 0 +3 db 25 focus error ac difference vfeacp 0 50 100 mv 26 ferr maximum output voltage h vfepph 2.3 - - v 27 ferr minimum output voltage l vfeppl - - 0.4 v 28 agc max gain gagc agc_equalize 16 19 22 db 29 agc eq gain geq 0 1 2 db 30 agc normal gain gagc2 3 6 9 db 31 agc compress ratio cagc 0 2.5 5 db 32 agc frequency fagc -1.5 0 2.5 db
rf amp & servo signal processor s1l922 5x 9 table 2. electrical characteristics (continued) no. inspection items symbols inspection block spec unit 33 terr sum voltage gain sf gtsf tracking error 16.5 19.5 22.5 db 34 terr sum voltage gain se gtse amplifier 16.5 19.5 22.5 db 35 terr sum voltage gain s2 gts2 22.5 25.5 28.5 db 36 terr gain voltage gain 1 gtef1 -1.5 0.5 2 db 37 terr gain voltage gain 2 gtef2 1 1.7 2.4 - 38 terr gain voltage gain 3 gtef3 1 1.3 1.6 - 39 terr gain voltage gain 4 gtef4 1 1.45 1.9 - 40 terr gain voltage gain 5 gtef5 1 1.55 2.1 - 41 terr gain voltage gain 6 gtef6 1 1.45 1.9 - 42 terr gain voltage gain 7 gtef7 1 1.45 1.9 - 43 terr balance gain gtee 10.5 13.5 16.5 db 44 terr balance mode 1 tbe1 1.0 1.05 1.1 - 45 terr balance mode 2 tbe2 1.0 1.05 1.1 - 46 terr balance mode 3 tbe3 1.0 1.05 1.1 - 47 terr balance mode 4 tbe4 1.0 1.25 1.5 - 48 terr balance mode 5 tbe5 1.0 1.20 1.4 - 49 terr balance mode 6 tbe6 1.0 1.3 1.75 - 50 terr ef voltage gain difference d gtef 10.0 13.0 16.0 db 51 terr maximum output voltage h vtpph 2.0 - - v 52 terr maximum output voltage l vtppl - - 0.7 v 53 apc psub voltage l apsl apc - - 1.0 v 54 apc psub voltage h apsh & 2.0 - - v 55 apc psub ldoff apslof laser 2.2 - - v 56 apc current drive h acdh control 1.35 - - v 57 apc current drive l acdl - - 1.35 v 58 lpc rf differential 1 lprf1 0.4 0.5 0.6 v 59 lpc rf differential 2 lprf2 0.4 0.5 0.6 v 60 lpc te differential lpte 0.4 0.5 0.6 v 61 mirror minimum operating frequency fmirb mirror - 550 900 hz 62 mirror maximum operating frequency fmirp 30 75 - khz 63 mirror am characteristic fmira - 400 600 hz 64 mirror minimum input voltage vmirl - 0.1 0.2 v 65 mirror maximum input voltage vmirh 1.8 - - v
s1l9225x rf amp & s ervo signal processor 10 table 2. electrical characteristics (continued) no. inspection items symbols inspection block spec unit 66 fok threshold voltage vfokt fok -420 -360 -300 mv 67 fok output voltage h vfohh 2.2 - - v 68 fok output voltage l vfokl - - 0.5 v 69 fok feeq. characteristic ffok 40 45 50 khz 70 defect bottom voltage fdfctb defect - 670 1000 hz 71 defect cutoff voltage fdfctc 2.0 4.7 - khz 72 defect minimum input voltage vdfctl - 0.3 0.5 v 73 defect maximum input voltage vdfcth 1.8 - - v 74 normal efm duty voltage 1 ndefmn efm slice -50 0 +50 mv 75 normal efm duty symmetry ndefma 0 5 10 % 76 normal efm duty voltage 3 ndefmh 0 +50 +100 mv 77 normal efm duty voltage 4 ndefml -100 -50 0 mv 78 normal efm minimum input voltage ndefmv - - 0.12 v 79 normal efm duty difference 1 ndefm1 30 50 70 mv 80 normal efm duty difference 2 ndefm2 30 50 70 mv 81 efm2 duty voltage 1 edefmn1 enhanced -50 0 +50 mv 82 efm2 duty voltage 2 edefmn2 efm slicer -50 0 +50 mv 83 efm2 duty symmetry edefma 0 5 10 % 84 efm2 duty voltage 3 edefmh1 0 +50 +100 mv 85 efm2 duty voltage 4 edefmh2 0 +60 +120 mv 86 efm2 duty voltage 5 edefml1 -100 -50 0 mv 87 efm2 duty voltage 6 edefml2 -120 -60 0 mv 88 efm2 minimum input voltage edefmv - - 0.12 v 89 fzc threshold voltage vfzc interface 35 69 100 mv 90 anti-shock detection h vatsch 7 32 67 mv 91 anti-shock detection l vatscl -67 -32 -7 mv 92 tzc threshold voltage vtzc -30 0 +30 mv 93 sstop threshold voltage vsstop -100 -65 -30 mv 94 tracking gain win t1 vtgwt1 200 250 300 mv 95 tracking gain win t2 vtgwt2 100 150 200 mv 96 tracking gain win i1 vtgwi1 250 300 350 mv 97 tracking gain win l2 vtgwi2 150 200 250 mv 98 tracking bal win t1 vtgw11 -50 0 +50 mv 99 tracking bal win t2 vtgw12 -40 0 +40 mv
rf amp & servo signal processor s1l922 5x 11 table 2. electrical characteristics (continued) no. inspection items symbols inspection block spec unit 100 vfrsh voltage vfrsh interface 0.35 0.5 0.65 v 101 reference voltage vref -100 0 +100 mv 102 reference current h irefh -100 0 +100 mv 103 reference current l irefl -100 0 +100 mv 104 f. servo off offset vosf1 focus servo -100 0 +100 mv 105 f. servo dac on offset vosf2 0 +250 +550 mv 106 f. servo auto offset vaof -65 0 +65 mv 107 f. servo auto istat vistat2 2.3 - - v 108 ferr febias status vfebias -50 0 +50 mv 109 f. servo loop gain gf 19 21.5 24 db 110 f. servo output voltage h vfoh 2.2 - - v 111 f. servo output voltage l vfol - - 0.5 v 112 f. servo oscillation voltage vfosc 0 +100 +185 mv 113 f. servo feed through gff - - -35 db 114 f. servo search voltage h vfsh +0.35 +0.50 +0.65 v 115 f. servo search voltage l2 vfsh2 +0.20 +0.25 +0.30 v 116 f. servo search voltage h2 vfsl2 -0.30 -0.50 -0.20 v 117 f. servo search voltage l vfsl -0.65 -0.50 -0.35 v 118 focus full gain gfsfg 40.0 42.5 45.0 db 119 f. servo ac gain 1 gfa1 19.0 23.0 27.0 db 120 f. servo ac phase 1 pfa1 30 60 90 deg 121 f. servo ac gain 1 gfa2 14.0 18.5 23.0 db 122 f. servo ac phase 1 pfa2 30 60 90 deg 123 f. servo muting gmutt - - -15 db 124 f. servo ac characteristic 1 gfac1 0.75 0.85 0.95 - 125 f. servo ac characteristic 2 gfac2 0.68 0.78 0.88 - 126 f. servo ac characteristic 3 gfac3 0.60 0.70 0.80 - 127 f. servo ac characteristic 4 gfac4 0.68 0.78 0.88 - 128 f. servo ac characteristic 5 gfac5 0.94 1.04 1.14 - 129 f. servo ac characteristic 6 gfac6 0.73 0.83 0.93 - 130 t. servo dc gain gto tracking 13.0 15.5 17.75 db 131 t. servo off offset vost1 servo -100 0 +100 mv 132 t. servo dac offset vtdac 150 320 550 mv 133 t. servo on offset vost2 -250 0 +250 mv
s1l9225x rf amp & s ervo signal processor 12 table 2. electrical characteristics (continued) no. inspection items symbols inspection block spec unit 134 t. servo auto offset vtaof tracking -50 0 +50 mv 135 t. servo oscillation vtosc servo 0 +100 +185 mv 136 t. servo atsc gain gatsc 17.5 20.5 23.5 db 137 t. servo lock gain glock 17.5 20.5 23.5 db 138 t. servo gain up gtup 17.5 20.5 23.5 db 139 t. servo output voltage h vtsh 2.2 - - v 140 t. servo output voltage l vtsl - - 0.5 v 141 t. servo jump h vtjh 0.35 0.5 0.65 v 142 t. servo jump l vtjl -0.65 -0.5 -0.35 v 143 t. servo dirc h vdirch 0.35 0.5 0.65 v 144 t. servo dirc l vdircl -0.65 -0.5 -0.35 v 145 t. servo output voltage l gtff - - -39 db 146 t. servo ac gain 1 gta1 9.0 12.5 16.5 db 147 t. servo ac phase 1 pta1 -140 -115 -90 deg 148 t. servo ac gain 1 gta2 17.5 21.5 25.5 db 149 t. servo ac phase 1 pta2 -195 -150 -100 deg 150 t. servo full gain gtfg 29.5 32 34.75 db 151 t. servo ac characteristic1 gtac1 0.59 0.69 0.90 - 152 t. servo ac characteristic2 gtac2 0.75 0.85 0.95 - 153 t. servo ac characteristic3 gtac3 0.65 0.75 0.85 - 154 t. servo ac characteristic4 gtac4 1.30 1.35 1.50 - 155 t. servo ac characteristic5 gtac5 1.15 1.25 1.35 - 156 t. servo ac characteristic6 gtac6 1.01 1.11 1.21 - 157 t. servo loop mutt tsmutt -250 0 +250 mv 158 t. servo loop mutt ac tsmtac 0 +50 +100 mv 159 t. servo int mutt m1 tsmtm1 0 +50 +100 mv 160 t. servo int mutt m2 tsmtm2 0 +50 +100 mv 161 t. servo int mutt m3 tsmtm3 0 +50 +100 mv 162 sl. servo dc gain gsl sled servo 10.5 12.5 14.5 db 163 sl. servo feed through gslf - - -34 db 164 sl. servo offset vsloff -100 0 +100 mv 165 sled forward kick vskh 0.45 0.60 0.75 v 166 sled reverse kick vskl -0.75 -0.60 -0.45 v 167 sled output voltage h vslh 2.2 - - v
rf amp & servo signal processor s1l922 5x 13 table 2. electrical characteristics (continued) no. inspection items symbols inspection block spec unit 168 sled output voltage l vsll sled servo - - 0.5 v 169 sled lock off vslock -100 0 100 mv 170 sp. servo 1x gain gsp clv servo 14.0 16.5 19.0 db 171 sp. servo 2x gain gsp2 19.5 23.0 27.0 db 172 sp. servo output voltage h vsph 2.2 - - v 173 sp. servo output voltage l vspl - - 0.5 v 174 sp. servo ac gain 1 gspa1 -7.0 -3.5 0 db 175 sp. servo ac phase 1 pspa1 -120 -90 -60 deg 176 sp. servo ac gain 2 gspa2 5.5 9.0 12.5 db 177 sp. servo ac phase 2 pspa2 -110 -80 -50 deg
s1l9225x rf amp & s ervo signal processor 14 operation description micom command $0x, $1x item address data istat output d7 d6 d5 d4 d3 d2 d1 d0 focus control 0 0 0 0 fs4 focus on fs3 gain down fs2 search on fs1 search up fzc tracking control 0 0 0 1 anti - shock brake - on tg2 gain set tg1 gain set atsc tracking gain setting according to anti-shock d7 d6 d5 d4 d3 d2 d1 d0 istat anti - shock lens. brake - on tg2 (d3 = 1) tg1 atsc 0 1 0 1 0 1 0 1 0 0 0 1 anti - shock off anti - shock on lens brake off lens brake on high - freq. gain down high - freq. gain normal gain normal gain up item hex as = 0 as = 1 tracking gain control tg2 tg1 tg2 tg1 tg1. tg2 = 1 ? gain up $10 0 0 0 0 $11 0 1 0 1 $12 1 0 1 0 $13 1 1 1 1 $14 0 0 0 0 $15 0 1 0 1 $16 1 0 1 0 $17 1 1 1 1 $13, $17, $1b, $1f (as0) $18 0 0 1 1 $13, $17, $18, $1c (as1) $19 0 1 1 0 mirror muting turns off when the tracking gain $1a 1 0 0 1 goes up $1b 1 1 0 0 $1c 0 0 1 1 $1d 0 1 1 0 $1e 1 0 0 1 $1f 1 1 0 0
rf amp & servo signal processor s1l922 5x 15 $2x d7 d6 d5 d4 d3 d2 d1 d0 istat 0 0 1 0 tracking servo mode sled servo mode operation of mode (tm1-tm7) mode tm7 tm6 tm5 tm4 tm3 tm2 tm1 tm1 $20 1 0 1 0 1 1 0 0 track. servo off $21 1 0 1 0 1 0 0 1 track. servo on $22 1 0 0 0 1 1 0 tm2 $23 1 1 1 0 1 1 0 0 sled. servo on $24 1 0 1 0 1 1 1 1 sled. servo off $25 1 0 1 0 1 0 1 tzc tm4 tm3 track. kick $26 1 0 0 0 1 1 1 0 0 fwd. jump $27 1 1 1 0 1 1 1 0 1 jump off $28 1 0 1 0 0 1 0 1 1 rev. jump $29 1 0 1 0 0 0 0 tm6 tm5 sled kick $2a 1 0 0 0 0 1 0 0 0 fwd kick $2b 1 1 1 0 0 1 0 0 1 kick off $2c 1 0 1 1 1 1 0 1 1 rev kick $2d 1 0 1 1 1 0 0 tm7 (jump) $2e 1 0 0 1 1 1 0 1 lens brake on $2f 1 0 0 1 1 1 0
s1l9225x rf amp & s ervo signal processor 16 dirc (direct 1 track jump) tracking condition item hex dirc = 1 dirc = 0 dirc = 1 tm 654321 654321 654321 tracking mode $20 000000 001000 000011 $21 000010 001010 000011 $22 010000 011000 100001 $23 100000 101000 100001 $24 000001 000100 000011 $25 000011 000110 000011 $26 010001 010100 100001 $27 100001 100100 100001 $28 000100 001000 000011 $29 000110 001010 000011 $2a 010100 011000 100001 $2b 100100 101000 100001 $2c 001000 000100 000011 $2d 001010 000100 000011 $2e 011000 000100 100001 $2f 101000 100100 100001 register $3x address focus search sled kick tracking jump d15 - d12 d11 d10 d9 d8 d7 d6 d5 0011 ps4 search+2 ps3 search+1 ps2 kick+2 ps1 kick+1 ps5 jump+1 ps6 jump 1/2 ps7 jump 1/4 d11 d10 focus search d9 d8 sled kick d7 d6 d5 tracking jump 0 0 1x (5u) 0 0 1x (10u) 0 0 0 0x (0u) 0 0 1 0.25x (1.25u) 0 1 2x (10u) 0 1 2x (20u) 0 1 0 0.50x (2.50u) 0 1 1 0.75x (3.75u) 1 0 3x (15u) 1 0 3x (30u) 1 0 0 1.00x (5.00u) 1 0 1 1.25x (6.25u) 1 1 4x (20u) 1 1 4x (40u) 1 1 0 1.50x (7.50u) 1 1 1 1.75x (8.75u) initial 0 0 0 0 1 0 0
rf amp & servo signal processor s1l922 5x 17 address focus servo gain fset offck d15-d12 d4 d3 d2 d1 d0 0011 focus gain 60k focus gain 120k fset1 9k fset2 18k d4 d3 $08 $0c d2 d1 equivalence resistance febias, focus servo 0 0 580k 180k 0 0 141k (535k) offset control 0 1 460k 60k 0 1 122k (464k) clock 1 0 520k 120k 1 0 131k (498k) 1: on 1 1 400k 0k 1 1 113k (430k) 0: off initial 0 0 1 1 1 select (first 8 bits of 16 bits) d15 d14 d13 d12 d11 d10 d9 d8 istat 0 0 1 1 focus servo search level control sled servo kick level control sstop ps4 ps3 ps2 ps1 search +2 search +1 kick +2 kick +1 data mode (level) search x1 $30xx-$33xx kick x1 $30xx, $34xx, $38xx, $3cxx search x2 $34xx-$37xx kick x2 $31xx, $35xx, $39xx, $3dxx search x3 $38xx-$3bxx kick x3 $32xx, $36xx, $3axx, $3exx search x4 $3cxx-$3fxx kick x4 $33xx, $37xx, $3bxx, $3fxx data s.x1, k.x1 s.x2, k.x2 s.x3, k.x3 s.x4, k.x4 $30xx $35xx $3axx $3fxx
s1l9225x rf amp & s ervo signal processor 18 auto-sequence mode address data 0 1 0 0 d3 d2 d1 d0 auto-sequence cancel 0 0 0 0 auto-focus 0 1 1 1 1-track jump 1 0 0 0: fwd 10-track jump 1 0 1 1: rev 2n-track jump 1 1 0 m-track jump 1 1 1 fast search 0 1 0 speed related command ($f00, f03) address data d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 0 0 0 0 1x speed ($f00, $f04, $08, $f0c) x x 0 0 2x speed ($f03, $f07, $f0b, $f0f) x x 1 1
rf amp & servo signal processor s1l922 5x 19 ram register set table 1. ram register set item data address d7 d6 d5 d4 d3 d2 d1 d0 blind a, e overflow. c $50xx 0.18ms 0.09ms 0.04ms 0.02ms brake. b 0.36ms 0.18ms 0.09ms 0.04ms fast f 23.2ms 11.6ms 5.80ms 2.90ms fast k 0.72ms 0.36ms 0.18ms 0.09ms ini. 1 0 0 0 1 0 0 0 control $51xx ps3x pstzc offs fzcoff sbad gsel mcc1 mcc2 register sstop on/off tzc on/off t. window on/off fzc on/off terr sum gain cdrw- win tgh mirror bottom mirror peak 0 off off off off dividex2 400mv ? 500 mv 1x 1x 1 on on on on sum 200 mv ? 300 mv 2x ( rec- ommend) 2x ( rec- ommend) ini. 1 1 1 1 1 0 0 0 control $52xx mga1 mga2 mga3 fgs1 fgs2 tgc1 tgc2 gefm register mirror gain1.5x mirror gain2x mirror bias s. f. servo dc gain f. servo ac gain t. servo ac gain t. servo dc gain efm. asy gain sel 0 normal normal off up up up normal 5x normal 1 up (recommend) up bias normal normal normal up 8x up ini. 1 1 0 1 1 1 0 0 control $53xx tzcs1 ec9 limits speak ivsel on/off tocd trsts register trcnt, tzc sel track i. setting 3 c1-flag sstop 44k, 88k sel. voltage current sel efm peaking t. servo offset c t. bal & gain reset 0 trcnt on sstop 88k voltage off reset reset 1 tzc off c1-flag 44k current on set set ini. 0 1 1 0 0 0 1 1 control $54xx dsp3 dsp2 dsp1 alock complete tasy efmmode tzcrc register flaghold 46.4ms flaghold 23.2ms flaghold 11.6ms lock on/off trcnt complete tes output double asy meth. tzc noise filter 0 0ms 0ms 0ms lock = 1 duty repeat f0k asy compen- sation tzc ori. 1 46.4ms 23.2ms 11.6ms lock 0, 1 complete tes vref tzc fil. ini. 1 0 0 1 1 1 1 0
s1l9225x rf amp & s ervo signal processor 20 table 1. ram register set (continued) item data address d7 d6 d5 d4 d3 d2 d1 d0 control $55xx fjts tcnt febias offset control register fast search trcnt positive offset negative offset teo output clock rate msb 10mv/step lsb msb 10mv/step lsb 0 t. jump 1:1 off off off on on on 1 t. mute 16:1 on on on off off off ini. 1 0 0 0 0 1 1 1 item data d7 d5 d5 d4 function ps3x * sstop pstzc * tzc offs * tbal. tgain fzcoff * fzc sstop on/off comparator on/off tzc on/off comparator on/off t.window on/off comparator on/off fzc on/off comparator on/off 0 off * off 0 output off * off 0 output off * off 0 output off * off 0 1 on * sstop input on on on output ini. 1 47k pull-up resistance 1 1 1 $51xx d3 d5 d5 d4 function sbad * tes output gsel * tgh window mcc1 * 2x mirror mcc2 * 2x mirror terr sum gain control cdrw-win tgh comparator input select mirror bottom detect strengthen mirror peak detect strengthen 0 1x sum 400mv ? 500 mv 1x 2x 1x 2x 1 1.25x sum 200 mv ? 300 mv 2x (recommend) 2x (recommend) ini. 1 0 0 0
rf amp & servo signal processor s1l922 5x 21 item data d7 d5 d5 d4 function mga1 * mirror input mga2 * mirror input mga3 * mirror input fgs1 * focus servo mirror gain1. 5x voltage level select mirror gain2x voltage level select mirror bias s. voltage level bias select f.servo dc gain dc gain select 0 normal 1:recommend normal 0: recommend off up 1 up up bias normal ini. 1 1 0 1 $52xx d3 d5 d5 d4 function fgs2 * focus servo mga2 * track servo tgc2 * track servo gefm * efm slice f.servo ac gain dc gain select mirror gain2x dc gain select t.servo dc gain dc gain select efm. asy gain sel asymmetry loop gain 0 up up normal 5x normal select 1 normal normal up 8x up ini. 1 1 0 0 item data d7 d5 d5 d4 function tzcs1 * track count ec9 *tracking limits * pin 30 speak * f.servo trcnt, tzc sel clock select track i. setting3 servo pole freq. select c1-flag sstop output select 44k, 88k sel. servo mute & efm slice 0 trcnt on sstop 0: sstop in 88k hold 1 tzc off c1-flag 1: c1-flag out 44k judgment ini. 0 1 1 0 clock select $53xx function ivsel * voltage, on/off * f.servo. tocd * tracking trsts * t.bal & current voltage sel current pick-up efm peaking t. servo mutt & efm slice t.servo offset c servo offset value t.bal & gainreset t.gain dac value 0 voltage type select off hold using reset reset reset reset 1 current mode setting on control set control set control ini. 0 0 1 1
s1l9225x rf amp & s ervo signal processor 22 item data d7 d6 d5 video-cd confrontation c1flag select signal d4 function dsp3 dsp2 dsp1 defect, cpeak c1flag control alock flaghold 46.4ms flaghold 23.2ms flaghold 11.6ms signal generator cycle select h: c1point 1, l: c1point 0 lock on/off according to 0 0 0 0 only defect time alock 1 0 0 1 defect + 11.6ms signal 2 0 1 0 defect + 23.2ms ssp lock 3 0 1 1 defect + 34.8ms 0: lock=1 control 4 1 0 0 defect + 46.4ms 1: lock 0,1 5 1 0 1 defect + 58.0ms by dsp $54xx 6 1 1 0 defect + 69.6ms 7 1 1 1 defect + 81.2ms ini. 1 0 0 d3 d5 d5 d4 function complete * trcnt tasy * pin 60 efmmode * efm mode tzcrc * control trcnt complete count value for tes output output select double asy meth. double asy mode tzc noise filter by tzc filter at 0 duty repeat micom fok asy requital control tzc ori. using tzc 1 complete move tes vref tzc fil. of trcnt ini. 1 1 1 0
rf amp & servo signal processor s1l922 5x 23 item data d7 d6 function fjts * tracking tcnt * trcnt count fast search teo output servo output at fast trcnt clock clock rate at micom 0 t.jump search 1:1 move 1 t.mutt 16:1 $55xx ini. 1 0 d5 d4 d3 d2 d1 d0 function febias offset control positive offset negative offset msb 10mv/step lsb output offset msb 10mv/step lsb output offset 0 0 0 0 0mv 0 0 0 -100mv 1 0 0 1 +15mv 0 0 1 -90mv 0 1 0 +30mv 0 1 0 -75mv 0 1 1 +45mv 0 1 1 -60mv 1 0 0 +60mv 1 0 0 -45mv 1 0 1 +75mv 1 0 1 -30mv 1 1 0 +90mv 1 1 0 -15mv 1 1 1 +100mv 1 1 1 0mv ini. 0 0 0 1 1 1
s1l9225x rf amp & s ervo signal processor 24 address hex d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 kick d $6xxx 11.6ms 5.80ms 2.90ms 1.45ms fast r 23.2ms 11.6ms 5.80ms 2.90ms pwm duty pd 8 4 2 1 pwm width pw 11.0ms 5.43ms 2.71ms 1.35ms ini. 0 1 1 1 1 0 1 0 0 0 1 0 2n tra. n m tra. m $7xxx 4096 2048 1024 512 256 128 64 32 16 8 4 2 fast search t $7xxx 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 ini. 0 0 0 0 0 0 1 1 1 1 1 1 brake point p $cxxx 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 ini. 0 0 0 0 0 0 1 1 1 0 0 0 trcnt count output comptlete $cxxx tcnt = 0 128 64 32 16 8 4 2 1 $55xx tcnt = 1 2048 1024 512 256 128 64 32 16 ini. 1 1 0 0 0 1 1 1 clv on/off register clv on, efm on $99x1~$99xf x x x x x x x 1 clv off, efm off $99x0 x x x x 0 0 0 0 ini 1 0 0 1 x x x x 0 0 0 0 notice. the actual value many be slightly different from the set value. a set value + 4 - 5 wdck b, d, e set value + 3 wdck c set value + 5 wdck n, m, t, p set value + 3 trcnt caution - among the 16 settings of pwm width 'pw' only one from d3, d2, d1, and d0 can be selected. (not 4bit combination) - more than 512 tracks are not recommended when 2n track and m track are used. (algorithm possesses problem generation) - because pwm duty 'pd' can have 1 - 2 errors, should be set to "set value + 2" - $5xxx's i/v sel command is ( 0: voltage pick-up configuration, 1: current type only) - t.rst - 0: tracking servo offset dac value reset cancel, 1: tracking servo offset dac value reset
rf amp & servo signal processor s1l922 5x 25 automatic control command tracking balance and gain control address address data istat trcnt d7 d6 d5 d4 d3 d2 d1 d0 tracking bal. $800x - $801x 0 0 0 b4 b3 b2 b1 b0 bal trcnt initial v. 0 1 1 1 1 tracking gain. $810x - $811x 0 0 0 g4 g3 g2 g1 g0 tgh tgl initial v. 1 0 0 0 0 tracking balance and gain control window data address d7 d6 d5 d4 d3 d2 d1 d0 istat trcnt t. gain t. bal f.s.o.c f.e.o.c intc intc2 intc3 dspmc $84xx tracking gain control window tracking balance control window f. servo offset control fe. bias offset control t. servo cpeak mute t. servo mirror mute f. servo cpeak mute c1 falg defect ref. $841 (f.err) $842 (f.ser) trcnt trcnt istat istat 0 250mv 200mv -10 ? - 15mv off off off off off 0.54ms 1 150mv 300mv -20 ? 20mv on on on on on 0.73ms initial 0 0 0 0 0 1 1 1 apc (automatic power control) address data d7 d6 d5 d4 d3 d2 d1 d0 ldon lpcoff alpc1 alpc2 apcl1 apcl2 ahold asel3 $85xx apc on/off lpc laser control on/off default (recommend) laser mediation control default (recommend) laser mediation control default (recommend) laser range control default (recommend) laser range control default (recommend) laser control hold default (recommend) laser control gain default (recommend) 0 on off off off off off hold 2x 1 off on on on on on off 1x initial 1 1 1 1 1 1 1 0 recommend default value ( d6 ? d7)
s1l9225x rf amp & s ervo signal processor 26 additional register set 1 data address d7 d6 d5 d4 d3 d2 d1 d0 f.ser.reset foksel monitor fsoc asel1 asel2 eqb eqr $86xx focus servo offset control reset trcnt output sel (monitor:1) except at gain control ($81xx) 0: fok 1: trcnt trcnt monitor select 1: fok, tgl trcnt 0:test output ferr. offset focus offset control step time setting 0:46.0ms 1:5.80ms laser control source laser control source agc eq agc gain up/normal d6 d5 istat2 0 0 test 0 1 fok(tgl) 1 0 test 1 1 trcnt(tgl) 0 reset fok test 46ms/step 1/2 eqi eqi 12ua up-13k 1 set trcnt fok, trcnt, tgl 5.8ms/step 1/3 eqi tes 20ua nor-7k initial 1 1 1 1 1 0 0 1 trcnt select is selected by the monitor (d1). with the tracking gain control command ($81xx), tgl is output, and the remaining becomes fok if they are 0 from the foksel bit. if they are 1, cout is output to trcnt. d5 bit priority over d6 bit, it related istat2 output. additional register set 2 address data d7 d6 d5 d4 d3 d2 d1 d0 - dirc rsts agcl2 agcl1 efmbc mt2 mt1 mt0 - $87xx dirc control febias reset agc size control d5 d5, d4 0 0 1.6v 0 1 1.45v 1 0 1.25v 1 1 1.0v efm double asy. revision 0 0 0 fsdfct * recom mend 0 0 1 fecmpo d5 d4 0 1 0 defect 1 1 0 1 1 mirror 1 0 0 cpeak 1 0 1 dfctint 1 1 0 balh 1 1 1 ball 0 enable reset on on off 1 disenable set off off on initial v. 1 1 0 0 0 1 1 1
rf amp & servo signal processor s1l922 5x 27 $8exx focus & tracking servo filter control command address data d7 d6 d5 d4 d3 d2 d1 d0 $8exx track. s freq. movement 0: low frequency 1: high frequency) f. servo phase shift 0: low frequency 1: high frequency clv freq. movement 0: low frequency 1: high frequency 0 on on on on on on on on 1 off off off off off off off off initial v. 1 0 1 1 0 1 1 0 $8fxx tracking servo offset control command address data d7 d6 d5 d4 d3 d2 d1 d0 $8f00 ? $8f1f x x x tracking servo offset control command 8f(000xxxxx) $8f1f ? $8f00 (-160mv ? +160mv) control window is used with the balance window and monitors the istat output because tracking offset of approximately +30mv - +50mv is ideal in the system, consider the control setting by raising to ($8f1f ? $8f00) 3 - 5 steps after controlling the offset to 0mv. consider the measure setting by $8010 command of tracking switch and $811f command of tracking gain switch after $24 command. initial v. 0 0 0 1 0 0 0 0
s1l9225x rf amp & s ervo signal processor 28 photo-diode i/v amp gain setting for cd-r and cd-rw data address d7 d6 d5 d4 rf & ferrgain rfo onlygain rfo total rwc1 1.0x rwc2 1.5x rwc3 2.0x rwc4 1.25x i/v amp equivalence input resistance at 55k gain rwc4 summing resistance rfo feed resistance rate 22k rfo loop total $82xx rfo & focus error gain rfo only 1 stage gain 2 stage gain rof total compared with of 0e 1 1 1 0 58.5k 1.06 10k 22k/10k=2.2 9.33 1.00 0f 1 1 1 1 58.5k 1.06 8k 22k/8k=2.75 11.66 1.25 06 0 1 1 0 91.5k 1.66 10k 22k/10k=2.2 14.61 1.56 07 0 1 1 1 91.5k 1.66 8k 22k/8k=2.75 18.26 1.96 0a 1 0 1 0 121.75k 2.21 10k 22k/10k=2.2 19.45 2.08 0b 1 0 1 1 121.75k 2.21 8k 22k/8k=2.75 24.31 2.60 02 0 0 1 0 154.75k 2.81 10k 22k/10k=2.2 24.73 2.65 03 0 0 1 1 154.75k 2.81 8k 22k/8k=2.75 30.91 3.31 0c 1 1 0 0 154.75k 2.81 10k 22k/10k=2.2 24.73 2.65 0d 1 1 0 1 154.75k 2.81 8k 22k/8k=2.75 30.91 3.31 04 0 1 0 0 187.75k 3.41 10k 22k/10k=2.2 30.00 3.21 05 0 1 0 1 187.75k 3.41 8k 22k/8k=2.75 37.51 4.02 08 1 0 0 0 218.00k 3.96 10k 22k/10k=2.2 34.84 3.73 09 1 0 0 1 218.00k 3.96 8k 22k/8k=2.75 43.56 4.66 00 0 0 0 0 251.00k 4.56 10k 22k/10k=2.2 40.33 4.32 01 0 0 0 1 251.00k 4.56 8k 22k/8k=2.75 50.16 5.37 0 up up up normal cd-rw mode set by 0, if more gain up set by 1 1 normal normal normal up and gain value is more big set by 8. initial 1 1 1 0
rf amp & servo signal processor s1l922 5x 29 tracking error cd-rw mode gain data address d3 d2 d1 d0 tracking error rfo total rwc6 1.0x rwc7 1.5x rwc8 2.0x rwc9 1.5x i/v amp equivalence resistance input resistance at 82k gain rwc9 difference resistance tracking feed resistance rate 22k terr loop total $82xx tracking error gain t.e diff- erence 1 stage gain 2 stage gain terr total compared with oe 0f 1 1 1 0 391k 1.06 30k 96k/30k=3.2 9.33 2.00 0e 1 1 1 1 391k 1.06 15k 22k/15k=6.4 11.66 1.00 07 0 1 1 0 583k 1.66 30k 96k/30k=3.2 14.61 2.98 06 0 1 1 1 583k 1.66 15k 22k/15k=6.4 18.26 1.49 0b 1 0 1 0 786k 2.21 30k 96k/30k=3.2 19.45 4.02 0a 1 0 1 1 786k 2.21 15k 22k/15k=6.4 24.31 2.01 03 0 0 1 0 979k 2.81 30k 96k/30k=3.2 24.73 5.01 02 0 0 1 1 979k 2.81 15k 22k/15k=6.4 30.91 2.50 0d 1 1 0 0 979k 2.81 30k 96k/30k=3.2 24.73 5.01 0c 1 1 0 1 979k 2.81 15k 22k/15k=6.4 30.91 2.50 05 0 1 0 0 1171k 3.41 30k 96k/30k=3.2 30.00 6.00 04 0 1 0 1 1171k 3.41 15k 22k/15k=6.4 37.51 3.00 09 1 0 0 0 1374k 3.96 30k 96k/30k=3.2 34.84 7.03 08 1 0 0 1 1374k 3.96 15k 22k/15k=6.4 43.56 3.51 01 0 0 0 0 1567k 4.56 30k 96k/30k=3.2 40.33 8.02 00 0 0 0 1 1567k 4.56 15k 22k/15k=6.4 50.16 4.01 0 up up up normal cd-rw mode set by 0 (4.01x) 1 normal normal normal up if gain value more big setting by 8 initial 1 1 1 0
s1l9225x rf amp & s ervo signal processor 30 photo-diode i/v amp gain setting and rfo offset control for cd-r and cd-rw. data address d7 d6 d5 d4 d3 d2 d1 d0 rwc5 rwc10 rfoc1 rfoc2 rfoc3 rfoc4 rfbc1 rfbc2 $83xx focus error related gain cd-rw related monitor output based on rfoc1 + rfoc2 + rfoc3 + rfoc4. priority order: rfoc2>rfoc4>rfoc1,rfoc3 rfamp offset control 0 down(0.5x) normal(1x) 1/2 rfo rfoc4 focus error rfoc3 normal normal 1 normal(1x) up(2x) eqi te gain tes rfoc1 down down initial 1 0 0 1 0 0 0 0 mode setting data data f.error gain data monitor output data rfo offset d7 d6 d5 d4 d3 d2 istat trcnt d1 d0 0 0 0.5 0 0 0 0 focus error focus error 0 0 0mv 0 1 1.0 0 0 0 1 1/2 rfo 1/2 rfo 0 1 0mv 1 0 1.0 0 0 1 0 tes tes 1 0 -100mv 1 1 2.0 0 0 1 1 1/2 rfo 1/2 rfo 1 1 -200mv 0 1 0 0 tgh tgl 0 1 0 1 tgh tgl 0 1 1 0 tgh tgl 0 1 1 1 tgh tgl 1 0 0 0 focus error focus error 1 0 0 1 eqi eqi 1 0 1 0 tes tes 1 0 1 1 eqi eqi 1 1 0 0 tgh tgl 1 1 0 1 tgh tgl 1 1 1 0 tgh tgl 1 1 1 1 tgh tgl cd-rw detect method there are four types of source signals in the method used to read the cd-rw disc. 1. focus error signal 2. tracking error summing signal (tes) 3. rfo 4. eqi tracking gain window outputs(tgh,tgl) are sent to istat1 and istat2 during focus search. 1 focus error the monitor output in the table above is set as the focus error output and the focus error output level comparison $81xx is sent to istat1 and istat2 to allow the micom to monitor the focus error output. after $81xx is sent, it possible to monitor because the tracking gain window comparator are used commonly. with search command ($47), if the intensity of radiation set its target, focus search level is 1vp-p, and peak value is 0.5v. as the table below, windows level transmit $84cx $513x command, istat1 monitored at 500mv. 2 tes set the tes in the table above and read the cd-rw disc the same way as focus error detect. 3 rfo set the rfo in the table above and read the cd-rw disc the same way as focus error detect. 4 eqi set the eqi in the table above and read the cd-rw disc the same way as focus error detect. istat output istat2 istat1 mode $517x $513x $844x 250mv 200mv 400mv a total of 6 tracking gain windows use $84xx and $51xx to $84cx 150mv 300mv 500mv read the cd and cd-rw disc.
rf amp & servo signal processor s1l922 5x 31 auto-sequence this function executes the chain of commands that execute auto-focus, track jump, and move. mlt latches the data at time l, and istat is l during auto-sequence. it output h upon. auto focus flow-chart focus search up focus servo on no yes no yes no yes auto focus end fok = h fzc = h fzc = l during blind "e" time set by register 5, fok and fzc executions repeat until they become "h". timing chart auto-focus receives the auto-focus command from the micom in the focus search down state and focus search up. the ssp becomes focus servo on when fzc changes to l after the internal fok rzc satisfy 'h', all the time set blind 'e' (register $5x). all the internal auto focus executes ended. and this status is sent to micom through the istat output. $47 latch blind time e fok, fzc -> h search up search down $02 $03 $03 $03 $08 internal status focus output fok mlt focus servo on fzc istat
s1l9225x rf amp & s ervo signal processor 32 1 track jump {$48(fwd), $49(rev)} flow-chart track jump sled servo off wait brake "b" no yes wait (blind a) track rev jump track, sled servo on 1 track jump end trcnt = forward jump when $48 and reverse jump when $49 wait using the wdck reference clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) repeat check of whether trcnt is continuously in "h" state with the wdck reference clock for the brake "b" time, set by register 5, at the trcnt rising edge. 1 track jump timing chart {$48(fwd), $49(rev) inside ( ) reverse} $47 ( $49) blind time a wait blind time b trcnt "h" tracking farward jump track servo on tracking revrese jump track servo on sled servo on sled servo off sled servo on $25 $28 ($2c) $28 ($2c) $2c ($28) $25 istat sled output track output trcnt mlt internal status receives $48 ($49) for 1 track jump and sets the blind and brake times through register $5x.
rf amp & servo signal processor s1l922 5x 33 10 track jump {$4a(fwd), $4b(rev)} flow-chart track fwd jump sled fwd kick trcnt = 5 no yes wait (blind a) track rev jump, sled fwd kick track, sled servo on no yes 10 track jump end c = over flow? foward jump & kick when $4a and reverse jump & kick when $4b. wait using the wdck reference clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) tracking reverse jump & sled forward kick when $4a and tracking forward jump & reverse kick when &4b. repeat check of trcnt 1's cycle with the wdck reference clock to determine if the cycle is long than the overflow "c" time, set by register 5. 10 track jump timing chart {$4a(fwd), $4b(rev) inside ( )reverse } $4a ( $4b) blind time a wait trcnt 5 count tracking forward jump track servo on tracking revrese jump track servo on sled servo on sled forward kick sled servo on $25 $2a ($2f) $2a ($2f) $2e ($2b) $25 istat sled output track output trcnt mlt over flow time c trcnt 1's time check fwd rev internal status 10 track jump executes the tracking forward jump up to trcnt 5track count and turns on the tracking and sled servos after a tracking reverse jump until trcnt 1's cycle is longer than the overflow 'c' time. this operation checks whether the actuator speed is sufficient to turn on the servo.
s1l9225x rf amp & s ervo signal processor 34 2n track jump flow-chart track fwd jump, sled fwd kick no yes wait (blind a) track rev jump, sled fwd kick wait (kick "d") no yes track servo on, sled fwd kick tracking & sled servo on 2n track jump end trcnt = n? c = over flow? foward jump & kick when $4c and reverse jump & kick when $4d. wait using the wdck reference clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) tracking reverse jump & sled forward kick when $4c and tracking forward jump & reverse kick when $4d. repeat check of trcnt 1's cycle with the wdck reference clock to determine if the cycle is longer than the overflow "c" time, set by register 5. when $4c, the sled forward kick continues for kick "d" time. when $4d, the sled reverse kick continues for kick "d" time.
rf amp & servo signal processor s1l922 5x 35 2n track jump timing chart {$4c(fwd), $4d(rev) inside ( ) reverse } $4c ( $4d) blind time a wait trcnt n count tracking forward jump track servo on tracking revrese jump track servo on sled servo on sled forward kick sled servo on $25+$17 $2a ($2f) $2a ($2b) $2e ($2b) $25+$18 istat sled output track output trcnt mlt over flow time c trcnt 1's cycle time check fwd rev c c kick time d sled fwd kick for d time q data read enable $26($27) internal status similar to 10 tracks and executes by adding sled kick by the amount of kick 'd' time and the servo turns on after lens brake starts.
s1l9225x rf amp & s ervo signal processor 36 m track jump {$4e(fwd), $4f(rev)} flow-chart track servo off, sled fwd kick no yes wait (blind a) tracking & sled servo on m track jump end trcnt = m? sled fwd kick when $4e and rev kick when $4f. wait using the wdck reference clock for blind "a" time, set by register 5. (1 wdck = 0.011ms) count trcnt with the clock for m amount, set by register 7. m track jump timing chart {$4e(fwd), $4f(rev) inside () reverse} $4e ( $4f) blind time a wait trcnt n count tracking servo off track servo on treck servo on sled servo on sled forward kick sled servo on $25 $22 ($23) $22 ($23) $22 ($23) $25 istat sled output track output trcnt mlt fwd rev internal status makes trcnt to clock and counts to the value of m count, set by register 7, to execute sled kick.
rf amp & servo signal processor s1l922 5x 37 fast search flow-chart track servo on, sled fwd kick wait (blind f) no yes track fwd jump, sled fwd kick wait (blind k) track fwd jump, sled fwd pwm kick no yes track servo on, sled rev kick wait (rev. kick "r") tracking & sled servo on fast search end trcnt = t? trcnt = p? sled forward kick when $44 and sled reverse kick when $45. tracking forward kick jump and sled forward kick when $44 and tracking reverse jump and sled reverse kick when $45 execute the above conditions until trcnt is the same as the brake point "p" count value, set by register 7. repeat checks trcnt, until trcnt equals t set by register 7, like the pd and pw set by register 6, pwms duty is decided with the pws pwm1 period width used as the period, and pds high. low duty used as standard 4 bits (number selected from 0 - 15) when $44, the sled forward kick continues for kick "r" time. when $45, the sled reverse kick continues for kick "r" time.
s1l9225x rf amp & s ervo signal processor 38 fast search timing chart {$44(fwd), $45(rev) inside () reverse} $44 ( $45) blind time f wait trcnt p count sled servo on tracking forward jump track servo on $25+$17 $26 ($27) $2a ($2f) $26 ($27) $25+$18 istat sled output track output trcnt mlt fwd rev blind k wait trcnt t count kick "r" walt sled rev kick sled servo on sled servo on sled forward kick $5xx1 tracking servo mutt sled servo kick internal status to note during use of auto-sequence 1. must send tracking gain up and brake on ($17) during 1, 10, 2n, track jump, and fast search. 2. before the auto-sequence mode, mlt becomes 'l' and sequence operation executes at the initial wdck falling edge after data latch. 3. during play, determine as fok and gfs, not istat. 4. tracking gain up, brake, anti-shock and foc us gain down are not executed in auto-sequence, and separate command must be provided. 5. if the auto-sequence does not operate as istat max time over, apply $40 and use after clearing the ssp internal state. 6. the above indicated wdck receives 88.2khz from dsp. (2x ? 176khz) 7. the auto-sequence internal trcnt and the actual trcnt are slightly different. 8. problems can be generated in the algorithm for 2n and m tracks if jump of more than 512 tracks are attempted; therefore, use them for less than 51 2 track jumps, if at all possible. 9. use the fast-search algorithm for more than 512 tracks, if possible. 10. when the track is moved by micom, the internal trcnt count setting is created by the $cxxx command, and complete and continuous complete signals are output to istat.
rf amp & servo signal processor s1l922 5x 39 tracking balance control concept in tracking balance control, the micom compares and monitors the previously set dc voltage window and the tracking error dc offset, extracted from the external lpf for automatic control. i/v amp fdl ft2 gain adjust 5bit arrary 5bit (b4-b0) from micom - te1 lpft lpf and logic d q ck mirror tzc trcnt tbal rho rlo e beam f beam f e + - + - rh rh vdc 5 bit arrary gain control istat2 istat1 summary of operation when the focus and spindle servos are on, tracking balance control turns off the tracking and servo loops to open the tracking loop, extracts the dc offset by sending the error signal, passed through the optical pick-up and tracking error amp, through the external lpf, then this offset to the previously set window comparator level, and then informs of the completion the balance control to the micom through the istat, when the dc offset of the tracking error amp in window is extracted. at this time, tracking e beam-side i/v amps gain is selected by micom, and the 5-bit resistance arrays resistance value is selected by the 5-bit control signal. the values that micom applies are 00000 ? 11111. if you select the switch, teso dc offset increases the (2.5v- d v) ? (2.5v + d v) one step at a time, to enter the pre-selected dc window level. when it enters that level, the balance adjust is completed, and the switch condition is latched at this time because the teso signal frequency is distributed up to 2khz, the dc offset that passed through the lpf is not a correct value, if a dc component exists, and therefore, micom monitors the window output when the teso signal frequency is above 1khz. at this time, the frequency check the trcnt pin. when tbal output is h, balance control is complete. vdc < rli s1l9225x rf amp & s ervo signal processor 40 ? rhi: high level threshold value ? rli: low level threshold value ? vdc: window comparator input voltage ? tbal: and gate output value of the window comparator output an example of tracking balance control out of $8000 ? $801f 32 steps, the upper and lower 32 steps are used. after receiving $8110 as the gain when the focus and tracking are on, the control flow checks trcnt frequency to see if the more than 7 trcnt entered during 10ms. if yes, it checks the istat, if no, it checks the number of trcnt three times and goes on to the istat check. repeats fail, it raises the balance switch by 1 step. if istat does not immediately go to h, it for 10 ms during istat check after which it check whether istat is h continuously for 10ms, is repeated three times. if the three repeats fail, it raises the balance switch by 1 step. the above wait 10 ms while running the system. it finds the average of the values obtained the three repeated execution of the entire above balance control. if only the balance values are from two of the three repeats, these values are averaged. if only two out of the three tries were successful in getting a balance value, average the two values. set as balance switch, this average value +2. this is because the balance for the system and the minus value for the dc is stable in the system. precision is important in balance adjust, and about 1+2 sec is spent as adjust time, which is accounted for. balance control flowchart 1 start - environment setting focus on $08 spindle on clv-s tracking off $20 sled off gain $8110 balance window level setting check to see if trcnt is 7 for 10ms istat = h? present control value +2 step then, adj end. b0 to b4 switch control balance adj. start $8000 other method - can balance adjust while moving tracks - $f03 easy to trcnt freq check in the 2x mode -10mv - +15mv $84 x0xx -20mv - +20mv $84 x1xx almost 20mv is istat = h? check if istat is h after waiting 10ms repeat 3 times change switch if failure after 3 repeats repeat 3 times change switch if failure after 3 repeats no yes yes no balance adj. switch incnease by 1 step $8000 -> $801f if finds the average of the values obtained the three repeated execution of the entire above bacance control. if only two out of the three tries ware successtial in getting a bacance value, average the two value.
rf amp & servo signal processor s1l922 5x 41 balance control flowchart 2 start environment setting - focus on $08 - spindle on clv-s - tracking off $20 - sled off gain $8110 balance window level seting trcnt freq is high enough? istat = h? end adj. b0 to b4 switch control balance adj. start $8000 other method - can balance adjust while moving tracks - $f03 easy to trcnt freq. check in the 2x mode balance adj. switch incnease by 1 step $8000 -> $801f -10mv - +15mv $84 x0xx -20mv - +20mv $84 x1xx no yes yes 1khz check no when tracking balance ? the balance adjust is from $8000 to $801f, and the swi tch mode is changed one step at a time by 16-bit data transmission. after adjustment, a separate latch pulse is not necessary. ? if the trcnt freq. is not high enough, the balance control can be adjusted at $f03 applied 2x mode . ? here, we have suggested tracking off status for the balance adjust, but the same amount of flow can be balance adjusted while in track move. ? among the 16 bit data, the tracking balance window setting level can be selected from 0: -10 mv ? +15mv 1: -20mv ? +20mv through the d6 bit. ? when the tracking balance adjust is complete, the tracking gain control starts.
s1l9225x rf amp & s ervo signal processor 42 tracking balance equivalent resistance tracking balance fixed resistance and parallel resistance variable resistance (5bit) data tsio offset f equi- valent res. e equi- valent res. 100k/ 5bit r 5bit equi- valence 35k 70k 140k 280k 560k comments $8000 391k 480k 15.22k 17.9k 1 1 1 1 1 $8001 391k 475k 15.6k 18.6k 1 1 1 1 0 $8002 + 391k 468k 16.1k 19.3k 1 1 1 0 1 $8003 391k 463k 16.5k 19.7k 1 1 1 0 0 $8004 391k 455k 17.2k 20.8k 1 1 0 1 1 $8005 391k 451k 17.6k 21.5k 1 1 0 1 0 $8006 391k 444k 18.3k 22.4k 1 1 0 0 1 $8007 391k 439k 18.9k 23.3k 1 1 0 0 0 $8008 391k 433k 19.5k 24.3k 1 0 1 1 1 $8009 391k 426k 20.4k 25.5k 1 0 1 1 0 $800a - 391k 421k 21.0k 26.6k 1 0 1 0 1 70k//35k = 23.3k 1 $800b 391k 415k 21.9k 28.0k 1 0 1 0 0 280k//140k = 93.3k 2 $800c 391k 409k 22.7k 29.4k 1 0 0 1 1 560k//280k = 186.6k 3 $800d 391k 403k 23.7k 31.1k 1 0 0 1 0 140k//35k = 28k 4 $800e 391k 397k 24.7k 32.9k 1 0 0 0 1 280k//35k = 31.1k 5 $800f 391k 391k 25.9k 35k 1 0 0 0 0 560k//35k = 32.9k 6 $8010 391k 385k 27.1k 37.2k 0 1 1 1 1 140k//70k = 46.6k 7 $8011 391k 380k 28.5k 39.9k 0 1 1 1 0 280k//70k = 56k 8 $8012 391k 374k 30.0k 43.0k 0 1 1 0 1 560k//70k = 62.2k 9 $8013 391k 368k 31.7k 46.6k 0 1 1 0 0 1//2 = 18.56k 10 $8014 391k 361k 33.9k 51.4k 0 1 0 1 1 10//560k = 17.96k $8015 391k 357k 35.8k 56k 0 1 0 1 0 $8016 391k 350k 38.3k 62.2k 0 1 0 0 1 $8017 391k 344k 41.1k 70k 0 1 0 0 0 $8018 391k 336k 44.5k 80.4k 0 0 1 1 1 $8019 391k 332k 48.4k 93.9k 0 0 1 1 0 $801a 391k 327k 52.8k 112k 0 0 1 0 1 $801b 391k 321k 58.3k 140k 0 0 1 0 0 $801c 391k 315k 65.1k 187k 0 0 0 1 1 $801d 391k 309k 73.6k 280k 0 0 0 1 0 $801e 391k 303k 84.8k 560k 0 0 0 0 1 $801f 391k 298k 100k 0k 0 0 0 0 0 252k 13k 26k f equivalence resistance 252k 13k 5bit e equivalence resistance
rf amp & servo signal processor s1l922 5x 43 tracking gain control concept i/v amp i/v amp 5bit (g4-g0) from micom - te1 lpft lpf and logic istat 2 (trcnt) istat 1 tgo tgh tgl e beam f beam f e + - + - arrary controlled by 5bit switch - te2 gli ghi vac 1k, 103 to micom operation summary tracking gain control is executed by comparing the previously set gain set value of the window with the only the pure ac component of the signal teso (dc+ac) , which was extracted the resistance divide of the tracking error amp output, passed through the lpf and dc offset . the resistance divide regulates the gain by changing the 5 bit resistance combination with micom command. the tracking gain control is executed under the balance control, the same of focus loop on, spindle servo on, tracking servo off and sled servo off and controls amount of optical pick-up reflection and tracking error amp gain. external lpf cut-off freq. is 1o 10hz - 100hz. the window comparator comparison level can be selected between +150mv - +300mv and +250mv - 200mv using the micom command. tgl outputs the +150mv and +250mv comparator outputs to trcnt. tgh outputs the +300mv and +200mv comparator outputs to istat. vac < gli s1l9225x rf amp & s ervo signal processor 44 window input tgh (pin19) tgl (pin18) ghi gli vac 1 2 3 tracking gain control ? in balance control, 16 bit data transmission changes the switch mode by 1step from $811f ? $8100, and , after adjustment, a separate latch pulse is not needed. ? the h duty check reference of tgl output of trcnt output is above 0.1ms. ? the most appropriate method is chosen among the 4 control modes listed besides the ones above for control. ? among the 16 bit data, the tracking balance window setting level can be selected from 0: +250mv (tgl) - +200mv (tgh), 1: +150mv (tgl) - +300mv (tgh) through the d7 bit. ? when the tracking gain adjust is complete, it enters the tracking & sled servo loop and toc read.
rf amp & servo signal processor s1l922 5x 45 gain control flowchart 1 start - environment setting focus on $08 spindle on tracking off $20 sled off gain window level setting trcnt = h? end adj. g0 to g4 switch control gain adj. start $83f separate environment setting is not required when controlling the gain after controlling balance +150mv - +300mv $84 1xxx +250mv - +200mv $84 0xxx yes no 32 tep reduction of gain adj. switch from $811f -> $8100 in gain control, the micom command from $811f ? $8100 successively executes the down command and goes status 1 to 2 ? 3. if it reaches status 2, control ends. ? gain control method 1 the micom monitors the tgl output of trcnt and, when it detects the output's h duty (0.1ms), ends. the window comparator level at this time is +150mv - +300mv. ? gain control method 2 the micom monitors the tgo output of istat and, when it detects the output's h duty (0.1ms), ends. the window comparator level at this time is +150mv - +300mv. ? gain control method 3 the micom monitors the tgl output of trcnt and, when it detects the output's h duty (0.1ms), ends. it changes the window comparator level at this time from +150mv - +300mv to +250mv - +200mv. then it re- monitors the tgl output of trcnt, and, if it detects the output's h duty (0.1ms), control ends. if it latches the middle command between the previous micom command value and latter command value, +200mv gain control becomes possible. ? gain control method 4 the micom monitors the tgl output of trcnt and, when it detects the output's h duty (0.1ms), it down the micom command by 1 and control ends. the window comparator level at this time is +150mv - +300mv. ? gain control method 5 gain control is set to 32 steps in total and gain window is set to +250mv. (that is, start from $811f and head toward $8110) after setting $811f, it monitors the trcnt to check whether five trcnts were detected for 10ms. if yes, control ends, and, if not, it as gain switch is lowered by 1 step. the above process is repeated three times and the average value obtained from this repetition set as the gain control switch.
s1l9225x rf amp & s ervo signal processor 46 gain control flowchart 2 start - environment setting focus on $08 spindle on tracking off $20 sled off balance window level setting are there 5 trcnt for 100ms? end adj. g0 to g4 switch control gain adj. start $811f separate environment setting is not required when controlling the gain after controlling balance +150mv - +300mv $84 1xxx +250mv - +200mv $84 0xxx yes no 32 tep reduction of gain adj. switch from $811f -> $8110 gain switch seting after averaging the 3 repeats
rf amp & servo signal processor s1l922 5x 47 tracking gain equivalent resistance tracking gain data terr gain terr gain 5bit gain ratio proportional resistance combined resistance 7.5k 7.5k 3.75k 2.0k 1k comments $811f 0.096 96k/32k 0.032 15.0k 0.5k 1 1 1 1 1 the gain at $811e 0.272 ? x 3.0 0.090 15.0k 1.5k 1 1 1 1 0 ratio is $811d 0.428 0.142 15.0k 2.5k 1 1 1 0 1 calculated in $811c 0.567 0.189 15.0k 3.5k 1 1 1 0 0 the tsio $811b 0.662 0.220 15.0k 4.25k 1 1 0 1 1 terminal. $811a 0.777 0.259 15.0k 5.25k 1 1 0 1 0 $8119 0.882 0.294 15.0k 6.25k 1 1 0 0 1 $8118 0.977 0.325 15.0k 7.25k 1 1 0 0 0 $8117 1.043 0.347 15.0k 8.0k 1 0 1 1 1 $8116 1.144 0.381 15.0k 9.25k 1 0 1 1 0 $8115 1.200 0.400 15.0k 10.0k 1 0 1 0 1 $8114 1.269 0.423 15.0k 11.0k 1 0 1 0 0 $8113 1.317 0.439 15.0k 11.75k 1 0 0 1 1 $8112 1.378 0.459 15.0k 12.75k 1 0 0 1 0 $8111 1.434 0.478 15.0k 13.75k 1 0 0 0 1 $8110 1.487 0.495 15.0k 14.75k 1 0 0 0 0 $810f 1.548 0.516 7.5k 8.0k 0 1 1 1 1 $810e 1.636 0.545 7.5k 9.0k 0 1 1 1 0 $810d 1.714 0.571 7.5k 10.0k 0 1 1 0 1 $810c 1.783 0.594 7.5k 11.0k 0 1 1 0 0 $810b 1.860 0.620 7.5k 12.25k 0 1 0 1 1 $810a 1.888 0.629 7.5k 12.75k 0 1 0 1 0 $8109 1.941 0.647 7.5k 13.75k 0 1 0 0 1 $8108 1.988 0.662 7.5k 14.75k 0 1 0 0 0 $8107 2.021 0.673 7.5k 15.50k 0 0 1 1 1 $8106 2.0625 0.6875 7.5k 16.50k 0 0 1 1 0 $8105 2.100 0.700 7.5k 17.50k 0 0 1 0 1 $8104 2.134 0.711 7.5k 18.50k 0 0 1 0 0 $8103 2.158 0.719 7.5k 19.25k 0 0 0 1 1 $8102 2.189 0.729 7.5k 20.25k 0 0 0 1 0 $8101 2.217 0.739 7.5k 21.25k 0 0 0 0 1 $8100 2.243 0.747 7.5k 22.25k 0 0 0 0 0
s1l9225x rf amp & s ervo signal processor 48 example of systam control power on disc tray check loading focus error febias automatic control start $8780+$87f0+$841 transfer replay disc change focus offset cancel automatic control start $08+$867+(200ms wait)+ $86f+$842 transfer tracking offset cancel start $8f1f -> $8f00 (istat->h) laser diode on ld on, p-sub $8560 transmission limit sw check focusing auto-focusing $47 transmission spindle servo loop on tracking & sled loop off $20 transmission tracking balance adjust tracking gain adjust toc read ok? disc 8/12cm check play back 100ms istat l -> h? 100ms istat l -> h? time 100ms maximum 100ms maximum 2s maximum 300ms maximum try count 3? laser off $85c0 transmission display (no disc) standby laser off $85c0 transmission display (error), tray open standby fail no yes pass no yes close open focus ok? fok h?
rf amp & servo signal processor s1l922 5x 49 febias offset control x1 x2 x4 x8 3k + - + - 160k 4k 32k 32k + - fcmpo 164k vb va 13 fseo vc febias offset control starts when it receives the febias offset control start command $841x from the micom. febias offset control ends when the focus error amp output above 1/2 vdd after the focus output with 1/2 vdd at the focus error amp final output terminal. the voltage per 1 step of the focus offset control is approximately 17mv. the 5bit resistance dac changes from 112mv up to - 112mv in 1 step, after which 1/2 step, approximately -8mv offset, is applied. the offset dispersion after febias offset control exists between -8mv - +8mv. the time per 1 step is 5.8ms; for 5 bits and total of 32 steps, the maximum required time is 256ms. hardware performs the control from minus offset to plus offset. the febias offset re-control is when 4bit dac is reset by $8780. and reset can be canceled only when the $87f0 applied d2 bit is changed from 0 ? 1. the febias dac latch block reset for electrostatics and system operation is reset by micom data and not by reset terminal, the system reset.
s1l9225x rf amp & s ervo signal processor 50 focus offset control 36 + - focus phase compensation - + ps 4 3 0 0 1 1 0 1 0 1 x1 x2 x3 x4 + - + - + - 35 08 25 26 12 14 09 3.6k 60k fzc i dfcti 48k fs4b fs3 580k fgd fdfct fsi 20k 470k 470k 40k fs2b 82k 40k 10k 50k 5k fs1 fset flb frch fem feo to digital vc focus offset control starts when it receives the focus offset control start command $842x from micom. focus offset control ends when the focus error amp output below 1.2 vdd after the focus output with 1/2 vdd at the focus error amp final output terminal. the voltage per 1 step of the focus offset control is approximately 40mv. the 4 bit resistance dac changes from 320mv up to -320mv in 1 step, after which 1/2 step, approximately - 20ms offset, is applied. the offset dispersion after focus offset control exists between -20mv - +20mv. the febias offset can be changed in 10mv step within the micom's 100mv range after focus offset control. the required per 1 step is 5.8ms; for 4 bits and total of 16 steps, the maximum required time is 128ms. also, lens-collision-sounds can be generated when adjusting the pick-up with a sensitive focus actuator, so the time division that uses 46 ms per step, spending a total of 736 ms, is used. the adjustment is carried out by hardware, and it goes from plus offset to minus offset. for focus offset readjust, 4-bit dac is reset by $867, and reset can be canceled only when the $86fx applied d2 bit is changed from 0 ? 1. the febias dac latch block reset for electrostatics and operation error is reset by micom data and not by reset terminal, the system reset.
rf amp & servo signal processor s1l922 5x 51 febias offset setting febias control the febias offset control is automatically controlled to 0mv and can be controlled to 100mv. after the focus offset automatic control ends after febias offset automatic control, the command sets the internal positive and negative offsets in 10mv units to the micom. rf summing amplifier appication the internal switch for the 1x and 2x filter select turns on when it is 1x and off, when 2x. the time constant to fit the set. the rf 1/v amp can be controlled to 0.5x 16step up to 1x - 8x cd-r and cdrw. the information related to cdr, cdrw disc detector is output as rfo level through the istat. the rfo offset control is installed to prevent rf level clipping during low rfo voltage and the rfo offset information is output to istat so that micom can know the rfo information. + - 50 49 pdc pda rfm 52 51 pdd pdb + - + - rf offset control 79 rfo 62 61 47k 47k 47k 47k cdrw gain sel 10k cdrw gain sel iv amp 10k rfm2 33pf 33pf 22k 2pf vc
s1l9225x rf amp & s ervo signal processor 52 rf equalize & agc modulator 3x gain amp hpf (3db: 50khz) i/v converter control range i * 10k full wave rectifier (rf peak envelope) iout = 2gm (vid/2) = gm * vid = (iref) * (vid/vt) = iref * (vp-vn)/vt if vn > vp vcagc increment (tanh (1-x)) if vn < vp vcagc decrement (tanh (1+x)) tanh 0.1 = 0.1 tanh 0.5 = 0.462 tanh 0.1 = 0.7 tanh 2.0 = 0.964 vref vp vn v = i/c (115pf) eqo-agc output vin (t) vcagc (t) vo (t) + - vin(t) = 0.73x (rfo) vo(t) = r6 (5.5k) r5 (7.5k) vin (t) tanh ( 2vt vcagc(t) ) the modulator output, which had the veqc's tanh term multiplied at the input, passes through the approximately 3x gain terminal to the arf pad. on the one hand, the output is - rectified as it passes through the hpf having 50khz pole frequency and follows the peak envelope the rf level. at this time, the pole frequency of the hpf is set to 50khz so that the 3t - 11t component can pass through without attenuation. the rf level peak value is integrated at the 's cap node after wave rectification. if this peak value is less than the already set voltage comparison, sinking current is output and, if not, sourcing current is output. the maximum peak value at this time is 10ua, which is i/v converted and applied as the modulator control voltage. under the sinking condition, the vcagc increases to 1outx10k and multiplied by tanh (1-x); the sourcing condition, vcagc decreases to iout x10k and multiplied by tanh (1+x), where x is (veqc/2vt). overall, after detecting the 3t and 11t levels by full-wave rectification, it is compared to tanh using the modulator and multiplied to the gain to realize the wave-form equalize. the above is related to the agc concept, which means that a specific rf level is always taken
rf amp & servo signal processor s1l922 5x 53 other block tracking error amplifier the side spot photo diode current input to terminals e and f passes through the e loop i-v and f loop i-v amps. it is then converted into voltage, in order to gain the difference signal in the tracking error amp. this portion can perform 0.5x 16 step gain control up to 1x-8x for cd-r and cd-rw. has the micom programming, which controls the balance by controlling gain at the e terminal and controls the gain at teio. 18 54 53 44 pde pdf teio istat2 + - cd-rw, cd gain sel cd-rw, cd gain sel 46 lpft2 win comp win comp b_ref_cn g_ref_cntr gain_up/d gain < 4: bal < 4:0 > 16r 8r 2r 4r r focus ok circuit focus ok circuit makes the timing window, which turns on the focus in the focus search state by "output" fok as l ? h if the rf level is above the reference after the difference in dc between and rfo terminals extracted and compared to the reference dc value. 64 63 eqi rfo + - + - 40k 40k 40k 57k 90k vc + 0.625v fokb
s1l9225x rf amp & s ervo signal processor 54 mirror circuit after amplifying the rfi signal, the mirror signal peak and bottom holds. peak hold can follow even at defect type traverse and bottom hold counts the tracks by following rf envelop at a jump. the mirror output is "l" on the disc track and "h" between tracks. even if above 1.4 ms is detected, it outputs "h". 64 eqi + - 17k 19k 38k peak and bottom hold + - + - + - 05 mcp mirror 80k 96k 17k 1.5k efm comparator the efm comparator makes the rf signal into a secondary signal. the asymmetry generated by a fault during disc production cannot be eliminated by only ac coupling, so control the standard voltage of the efm comparator to eliminate it. 02 + - 40k efmi - rf double asymmetry conection - efmi peak prevention system - asymmetry hold system - asymmetry gain control 27 asy 28 29 efm2 efm x5
rf amp & servo signal processor s1l922 5x 55 defect circuit after rfo signal inversion, bottom hold is carried out using only 2. except, the bottom hold of holds the coupling level just before the coupling. differentiate this with the coupling, then level shift it. compare the signals to either direction to generate the defect detect signal. 63 rfo + - 37.5k 75k 75k bottom envelope + - 04 dcc2 defect bottom envelope 06 dcb 03 dcc1 28k vc vc+0.6254v 43k apc circuit when the laser diode operates in electrostatic field, the laser output temperature highly negative so the monitor photo diode controls the laser output at a fixed level. the laser control system is installed to absorb the deviation of the disc reflection. system controls the laser power using the tracking summing signal of the side beam to a fixed laser output. 48 pd 47 ld + - + - laser control ldon 5k 5k 55k 0.25k 55k 5k 55k
s1l9225x rf amp & s ervo signal processor 56 center voltage generation circuit the center voltage is made by using the resistance divide. + - 30k vref 55 30k rf equalize circuit the agc block, which maintains the rf peak to peak level, possess the 3t gain boost. it detects the rf envelop and compares it to the reference voltage to control the gain. receives the rf output to stabilize the rf level to 1vpeak-peak, which is applied to the efm slice input. 64 eqi 37 eqc equalize vca 01 eqo atsc the detection circuit for shock tracking gain up is composed of the window comparator. 42 atsc bpf + - + - tracking gain up
rf amp & servo signal processor s1l922 5x 57 focus servo if the focus servo loop phase has been compensated, the focus servo loop mutts if the defect is. the focus error signal at this time is differentiated by the 0.1uf capacitor to be connected to the terminal and the 470kohms resistance and is output es through the servo loop. therefore, the focus output is held to value before the defect error during defect. the fset terminal changes the at which the focus loop compensation is at its maximum. if the resistance to vdda connected to the terminal, the phase compensation frequency is changed 1.2khz below, and gnd connected to the terminal, the frequency is changed 1.2khz above. during focus search, fs4 turns on to cutoff the error signal and to output the focus search signal through the feo. when the focus is on, fs2 turns on, and the focus error signal input through the fsi is output through the loop to the output pin. 36 + - focus phase compensation - + ps 4 3 0 0 1 1 0 1 0 1 x1 x2 x3 x4 + - + - + - 35 08 25 26 12 14 09 3.6k 60k fzc i dfcti 48k fs4b fs3 580k fgd fdfct fsi 20k 470k 470k 40k fs2b 82k 40k 10k 50k 5k fs1 fset flb frch fem feo to digital vc
s1l9225x rf amp & s ervo signal processor 58 tracking servo the tracking servo phase compensate the tracking servo loop and differentiates the tracking error signal, after which it outputs the signal through the servo loop. tgu exchanges the tracking gain up/down time constant. as in the focus loop, the phase compensation peak frequency is varied by the fset terminal. if the resistance connected to the fset terminal changes, the op amp dynamic range offeset changes also. 41 09 53 teio fset 90k teo tracking phase compensation 16 tgu tlpfi dfcti 680k + - 40 tem 10k tm7 68p f 680k tg1b 10k 110k 82k tm1 470k tg2b tm4 tm3 the tm7 switch is a brake switch which turns the tracking loop on/off when the actuator is unstable after a jump. after the servo jumps 10 tracks, the servo circuit leaves the linear range and the actuator sometimes pursues the unstable track, preventing unnecessary jumps from undesired tracking errors. as the terminal which controls the tracking servo loop's high frequency gain, the tgu terminal controls the desired frequency range of the gain through the external cap.
rf amp & servo signal processor s1l922 5x 59 sled servo this servo differentiates the tracking servo and moves the pick-up. it also outputs the sled kick voltage to make a track jump in the sled axis during track movement. 39 + - 37 slm tm6 tm7 38 slo tm2 ps 2 1 0 0 1 1 0 1 0 1 x1 x2 x3 x4 slp spindle servo & low pass filter the 200hz lpf, composed of an external 20kohms resistance and 0.33uf cap, eliminiates the high frequency carrier component. + - 33 spdlm 34 spdlo 100k + - 09 fset 25 clvi 50k fvco double speed 220k 22k 22k 220k 220k 220k
s1l9225x rf amp & s ervo signal processor 60 mirror & cpeak mute (use only for tracking mute ) used against abex-725a, this circuit processes the tracking mutting when mirror is detected. (no recommend) the tracking mutting when efm duty is above 22t after it is checked. mute does not operate in the following four cases. ? micom tracking gain up command transmission (tg1, tg2 = 1) ? anti-shock detection (atsc) ? lock falls to l ? defect detection trcnt output trcnt is output of mirror and tzc. mirror is the track movement detection output of the main beam; tzc is the track movement detection output of the side beam. trcnt receives these two inputs to determine whether the present pick-up is moving from the inside to the outside or from the outside to the inside. it is used at $17 tracking brake operation. mirror tzc inverter delay tzc edge detection. d q ck trcnt output tzc rising, falling edge mirror output.

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